Keynote Addresses

Keynote I

Boosting Productivity and Robustness in the SysMoore with a Triple-play of Hyperconvergency, Analytics, and AI Innovations

Speaker: Shankar Krishnamoorthy

Affiliation: Synopsys, USA

The SysMoore Era can be characterized as the widening gap between classic Moore’s Law scaling and increasing system complexity. System-on-a-chip complexity has now fallen by the wayside to systems-of-chips with the need for smaller process nodes, and multi-die integration. With engineers now handling not just larger chip designs but systems comprised of multiple chips, the focus on user productivity and design robustness becomes a major factor in getting designs to market in the fastest time and with the best possible PPA. Combining a hyperconvergent design flow with smart data analytics and AI-based solution space exploration provides a huge benefit to the engineer tasked with completing these systems. In this presentation outlines the challenges and the road to a triple-play solution that gets design engineers out of their late design-cycle jams.

Keynote II

Powering a Quantum Future through Quantum Circuits

Speaker: Jerry M. Chow

Affiliation: IBM, USA

As the field of quantum computing continues to mature, it becomes critical to drive progress in technologies for quantum computing systems through key metrics - scale, quality, and speed. Pushing on these dimensions enables us to achieve a path to quantum advantage in a practical frictionless fashion. I will overview the recent development of superconducting quantum computing systems and the technological advances by IBM that enabled us to scale superconducting qubits to our latest 127-qubit Eagle processor while also describing our efforts to continue improving the underlying quality of the devices, setting the foundational elements for our roadmap. I will also describe the efforts to expand the ecosystem through open source software with Qiskit, and appealing to a broad set of developers from hardware design all the way to applications research as we continue to drive a future for the consumption of quantum circuits.

Keynote III

EDA Opportunities for Future HPC and 3D IC Integration

Speaker: Ken Wang

Affiliation: TSMC, Taiwan

In the AI era of computing, it is opening lots of opportunities for semiconductor and EDA industries. More chips are built with customized AI-accelerators and parallel processing GPU. These demands will need High-Performance-Computing (HPC) technology to support and enable the implementations under a restricted power consumption. Technologies like MIM (Metal-Insulator-Metal), std cell designs architecture, and metal routing techniques are introduced to achieve HPC requirement. Also, more computing logics are integrated into a smaller yet more powerful system. The trend of this integration already happened with 2.5D chip or package design. Now, 3D IC design and fabrication has just begun and will be the future trend. 3D IC design flow examples and EDA challenges are summarized in this presentation.

Last Updated on: December 17, 2021