The 27th Asia and South Pacific Design Automation Conference
Technical Program

Remark:

Full presentation videos including Regular Sessions, Special Sessions, Designers' Forum, and University Design Contest are available on demand from January 10 to January 28, 2022.
The official conference is held online according to the time table below. For Regular Sessions, Special Sessions, and University Design Contest, pitch talk videos are played which is followed by live Q&A via WebEx.
Time zone is TST (=UTC+8:00)
The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, January 17, 2022

Room 1	Room 2	Room 3
T1 Tutorial-1 9:00 - 12:00	T2 Tutorial-2 9:00 - 12:00	T3 Tutorial-3 9:00 - 12:00
T4 Tutorial-4 13:30 - 16:30	T5 Tutorial-5 13:30 - 16:30	T6 Tutorial-6 13:30 - 16:30

Tuesday, January 18, 2022

Room A	Room B	Room C	Room D	Room E
1K (Room S) Opening and Keynote Session I 8:20 - 10:00
1A University Design Contest-1 10:00 - 10:35	1B (SS-1) New Advances towards Building Secure Computer Architectures 10:00 - 10:35	1C Research Paradigm in Approximate and Neuromorphic Computing 10:00 - 10:35	1D New Design Techniques for Emerging Challenges in Microfluidic Biochips 10:00 - 10:35	1E Advances in Machine Learning Assisted Analog Circuit Sizing 10:00 - 10:35
2A University Design Contest-2 10:35 - 11:10	2B (SS-2) Analog Circuit and Layout Synthesis: Advancement and Prospect 10:35 - 11:10	2C Low-cost and Memory-Efficient Deep Learning 10:35 - 11:10	2D High-level Verification and Application 10:35 - 11:10	2E Design for Manufacturing and Signal Integrity 10:35 - 11:10
3A (DF-1) Key Drivers of Global Hardware Security 11:10 - 11:55	3B Analysis and optimization for timing, power, and reliability 11:10 - 11:55	3C Advanced Machine Learning with Emerging Technologies 11:10 - 11:55	3D Software Solutions for Heterogeneous Embedded Architectures 11:10 - 11:55

Wednesday, January 19, 2022

Room A	Room B	Room C	Room D
2K (Room S) Keynote Session II 9:00 - 10:00
4A (SS-3) Technology Advancements inside the Edge Computing Paradigm and using the Machine Learning Techniques 10:00 - 10:35	4B Recent Advances in Placement Techniques 10:00 - 10:35	4C Emerging Trends in Stochastic Computing 10:00 - 10:35	4D Efficient Techniques for Emerging Applications 10:00 - 10:35
5A (DF-2) Compiler and Toolchain for Efficient AI Computation 10:35 - 11:10	5B Moving frontiers of test and simulation 10:35 - 11:10	5C Optimizations in Modern Memory Architecture 10:35 - 11:10	5D Novel Boolean Optimization and Mapping 10:35 - 11:10
6A (DF-3) AI for Chip Design and Testing 11:10 - 11:45	6B Towards Reliable and Secure Circuits: Cross Perspectives 11:10 - 11:45	6C Accelerator Architectures for Machine Learning 11:10 - 11:45	6D Quantum and Reconfigurable Computing 11:10 - 11:45
1W (Room W) Cadence Training Workshop 13:30 - 16:30

Thursday, January 20, 2022

Room A	Room B	Room C	Room D
3K (Room S) Keynote Session III 9:00 - 10:00
7A (SS-4) Reshaping the Future of Physical and Circuit Design, Power and Memory with Machine Learning 10:00 - 10:35	7B Advances in Analog Design Methodologies 10:00 - 10:35	7C Low-Energy Edge AI Computing 10:00 - 10:35	7D Emerging Technologies in Embedded Systems and Cyber-Physical Systems 10:00 - 10:35
8A (DF-4) Empowering AI through Innovative Computing 10:35 - 11:10	8B Advances in VLSI Routing 10:35 - 11:10	8C Machine Learning with Crossbar Memories 10:35 - 11:10	8D High Level Synthesis, CGRA mapping and P&R for hotspot mitigation 10:35 - 11:10
9A (SS-5) Artificial Intelligence on Back-End EDA: Panacea or One-Trick Pony? 11:10 - 11:45	9B Side Channel Leakage: Characterization and Protection 11:10 - 11:45	9C Emerging Non-volatile Memory-based In-Memory Computing 11:10 - 11:45	9D System Level Design of Learning Systems 11:10 - 11:45

DF: Designers' Forum, SS: Special Session

List of papers

Remark:

Full presentation videos including Regular Sessions, Special Sessions, Designers' Forum, and University Design Contest are available on demand from January 10 to January 28, 2022.
The official conference is held online according to the time table below. For Regular Sessions, Special Sessions, and University Design Contest, pitch talk videos are played which is followed by live Q&A via WebEx.
Time zone is TST (=UTC+8:00)
The presenter of each paper is marked with "*".

Monday, January 17, 2022

[To Session Table]

Session T1 Tutorial-1
Time: 9:00 - 12:00, Monday, January 17, 2022
Location: Room 1

T1-1

Title	(Tutorial) IEEE CEDA DATC RDF and METRICS2.1: Toward a Standard Platform for ML-Enabled EDA and IC Design
Author	Jinwook Jung (IBM Research, USA), Andrew B. Kahng, Seungwon Kim, Ravi Varadarajan (UCSD, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T2 Tutorial-2
Time: 9:00 - 12:00, Monday, January 17, 2022
Location: Room 2

T2-1

Title	(Tutorial) Low-bit Neural Network Computing: Algorithms and Hardware
Author	Zidong Du (Chinese Academy of Sciences, China), Haojin Yang (Hasso-Plattner-Institute, Germany), Kai Han (Huawei Technology, China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T3 Tutorial-3
Time: 9:00 - 12:00, Monday, January 17, 2022
Location: Room 3

T3-1

Title	(Tutorial) Side Channel Analysis: from Concepts to Simulation and Silicon Validation
Author	Makoto Nagata (Kobe Univ., Japan), Lang Lin (ANSYS Inc, USA), Yier Jin (Univ. of Florida, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T4 Tutorial-4
Time: 13:30 - 16:30, Monday, January 17, 2022
Location: Room 1

T4-1

Title	(Tutorial) New Techniques in Variational Quantum Algorithms and Their Applications
Author	Tamiya Onodera, Atsushi Matsuo, Rudy Raymond (IBM Research, Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T5 Tutorial-5
Time: 13:30 - 16:30, Monday, January 17, 2022
Location: Room 2

T5-1

Title	(Tutorial) Towards Efficient Computation for Sparsity in Future Artificial Intelligence
Author	Fei Sun (Alibaba Group, China), Dacheng Liang (Biren Technology, China), Yu Wang, Guohao Dai (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T6 Tutorial-6
Time: 13:30 - 16:30, Monday, January 17, 2022
Location: Room 3

T6-1

Title	(Tutorial) Scan-based DfT: Mitigating its Security Vulnerabilities and Building Security Primitives
Author	Aijiao Cui (Harbin Inst. of Tech., China), Gang Qu (Univ. of Maryland, USA)
Detailed information (abstract, keywords, etc)

Tuesday, January 18, 2022

[To Session Table]

Session 1K Opening and Keynote Session I
Time: 8:20 - 10:00, Tuesday, January 18, 2022
Location: Room S
Chair: Ting-Chi Wang (National Tsing Hua Univ., Taiwan)

1K-1 (Time: 8:20 - 9:00)

Title

ASP-DAC 2022 Opening:
1. Welcome by GC (Prof. Ting-Chi Wang)
2. Welcome by SC-Chair (Prof. Shinji Kimura)
3. Program Report by TPC Chair (Prof. Masanori Hashimoto)
   3-1. Best Paper Award Presentation (Dr. Gi-Joon Nam)
   3-2. 10-Year Retrospective Most Influential Paper Award Presentation (Dr. Gi-Joon Nam)
4. Designers' Forum Report by DF Co-Chairs (Prof. Hung-Pin Wen and Prof. Kai-Chiang Wu)
5. Design Contest Report by UDC Co-Chair (Prof. Ing-Chao Lin)
   5.1 UDC Award Presentation (Prof. Ing-Chao Lin)
6. Student Research Forum Report by SRF Chair (Prof. Lei Jiang)
7. IEEE CEDA Awards by CEDA President (Dr. Gi-Joon Nam)
   7.1 CEDA Outstanding Service Recognition (Dr. Gi-Joon Nam)
8. Welcome message for ASP-DAC 2023 by 2023GC (Prof. Atsushi Takahashi)

Detailed information (keywords, etc)

1K-2

Title	(Keynote Address) Boosting Productivity and Robustness in the SysMoore with a Triple-play of Hyperconvergency, Analytics, and AI Innovations
Author	*Shankar Krishnamoorthy (Synopsys, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1A University Design Contest-1
Time: 10:00 - 10:35, Tuesday, January 18, 2022
Location: Room A
Chairs: Ing-Chao Lin (National Cheng Kung Univ., Taiwan), Tsung-Te Liu (National Taiwan Univ., Taiwan)

Best Design Award
1A-1

Title	A 0.5 mm² Ambient Light-Driven Solar Cell-Powered Biofuel Cell-Input Biosensing System with LED Driving for Stand-Alone RF-Less Continuous Glucose Monitoring Contact Lens
Author	*Guowei Chen, Xinyang Yu, Yue Wang, Tran Minh Quan, Naofumi Matsuyama, Takuya Tsujimura, Kiichi Niitsu (Nagoya Univ., Japan)
Page	pp. 1 - 2
Detailed information (abstract, keywords, etc)
Slides

1A-2

Title	A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna Array
Author	*Taikun Ma, Wei Deng, Haikun Jia (Tsinghua Univ., China), Yejun He (Shenzhen Univ., China), Baoyong Chi (Tsinghua Univ., China)
Page	pp. 3 - 4
Detailed information (abstract, keywords, etc)

1A-3

Title	A 5.2GHz RFID Chip Contactlessly Mountable on FPC at Any 90-Degree Rotation and Face Orientation
Author	*Reiji Miura, Saito Shibata, Masahiro Usui, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda (Univ. of Tokyo, Japan)
Page	pp. 5 - 6
Detailed information (abstract, keywords, etc)
Slides

1A-4

Title	A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients
Author	*Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang (National Chung Cheng Univ., Taiwan), Chun-Ming Huang (Taiwan Semiconductor Research Institute, Taiwan), Ying-Hui Lai (National Yang Ming Chiao Tung Univ., Taiwan), Chingwei Yeh, Jinn-Shyan Wang (National Chung Cheng Univ., Taiwan)
Page	pp. 7 - 8
Detailed information (abstract, keywords, etc)

1A-5

Title	A Side-Channel Hardware Trojan in 65nm CMOS with 2µW precision and Multi-bit Leakage Capability
Author	*Tiago Perez, Samuel Pagliarini (Tallinn Univ. of Tech. (TalTech), Estonia)
Page	pp. 9 - 10
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 1B (SS-1) New Advances towards Building Secure Computer Architectures
Time: 10:00 - 10:35, Tuesday, January 18, 2022
Location: Room B
Chair: Aijiao Cui (Harbin Inst. of Tech., China)

1B-1

Title	(Invited Paper) SC-K9: A Self-synchronizing Framework to Counter Micro-architectural Side Channels
Author	*Hongyu Fang, Milos Doroslovacki, Guru Venkataramani (George Washington Univ., USA)
Page	pp. 11 - 18
Detailed information (abstract, keywords, etc)
Slides

1B-2

Title	(Invited Paper) CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security
Author	*Zihan Xu, Lingfeng Yin, Yongqiang Lyu, Haixia Wang (Tsinghua Univ., China), Gang Qu (Univ. of Maryland, USA), Dongsheng Wang (Tsinghua Univ., China)
Page	pp. 19 - 24
Detailed information (abstract, keywords, etc)
Slides

1B-3

Title	(Invited Paper) Lightweight and Secure Branch Predictors against Spectre Attacks
Author	*Congcong Chen, Chaoqun Shen, Jiliang Zhang (Hunan Univ., China)
Page	pp. 25 - 30
Detailed information (abstract, keywords, etc)
Slides

1B-4

Title	(Invited Paper) Computation-in-Memory Accelerators for Secure Graph Database: Opportunities and Challenges
Author	*Md Tanvir Arafin (Morgan State Univ., USA)
Page	pp. 31 - 36
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 1C Research Paradigm in Approximate and Neuromorphic Computing
Time: 10:00 - 10:35, Tuesday, January 18, 2022
Location: Room C
Chairs: Xunzhao Yin (Zhejiang Univ., China), Lang Feng (Nanjing Univ., China)

1C-1

Title	HEALM: Hardware-Efficient Approximate Logarithmic Multiplier with Reduced Error
Author	*Shuyuan Yu, Maliha Tasnim, Sheldon Tan (Univ. of California, Riverside, USA)
Page	pp. 37 - 42
Detailed information (abstract, keywords, etc)
Slides

Best Paper Candidate
1C-2

Title	DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification
Author	*Dehua Liang, Jun Shiomi, Noriyuki Miura (Osaka Univ., Japan), Hiromitsu Awano (Kyoto Univ., Japan)
Page	pp. 43 - 49
Detailed information (abstract, keywords, etc)
Slides

1C-3

Title	Thermal-aware Layout Optimization and Mapping Methods for Resistive Neuromorphic Engines
Author	*Chengrui Zhang (ShanghaiTech Univ./Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, China), Yu Ma (ShanghaiTech Univ./Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, China), Pingqiang Zhou (ShanghaiTech Univ./Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, China)
Page	pp. 50 - 55
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 1D New Design Techniques for Emerging Challenges in Microfluidic Biochips
Time: 10:00 - 10:35, Tuesday, January 18, 2022
Location: Room D
Chairs: Hailong Yao (Tsinghua Univ., China), Xing Huang (Tech. Univ. of Munich, Germany)

1D-1

Title	NR-Router: Non-Regular Electrode Routing with Optimal Pin Selection for Electrowetting-on-Dielectric Chips
Author	*Hsin-Chuan Huang, Chi-Chun Liang (National Tsing Hua Univ., Taiwan), Qining Wang (Univ. of California, Los Angeles, USA), Xing Huang, Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Chang-Jin Kim (Univ. of California, Los Angeles, USA)
Page	pp. 56 - 61
Detailed information (abstract, keywords, etc)
Slides

1D-2

Title	Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults
Author	*Jian-De Li, Sying-Jyan Wang (National Chung Hsing Univ., Taiwan), Katherine Shu-Min Li (National Sun Yat-sen Univ., Taiwan), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan)
Page	pp. 62 - 67
Detailed information (abstract, keywords, etc)
Slides

1D-3

Title	Improving the Robustness of Microfluidic Networks
Author	*Gerold Fink, Philipp Ebner, Sudip Poddar, Robert Wille (Johannes Kepler Univ. Linz - Institute for Integrated Circuits, Austria)
Page	pp. 68 - 73
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 1E Advances in Machine Learning Assisted Analog Circuit Sizing
Time: 10:00 - 10:35, Tuesday, January 18, 2022
Location: Room E
Chairs: Chien-Nan Jimmy Liu (National Yang Ming Chiao Tung Univ., Taiwan), Fan Yang (Fudan Univ., China)

Best Paper Candidate
1E-1

Title	An Efficient Kriging-based Constrained Multi-objective Evolutionary Algorithm for Analog Circuit Synthesis via Self-adaptive Incremental Learning
Author	*Sen Yin, Wenfei Hu, Wenyuan Zhang, Ruitao Wang, Jian Zhang, Yan Wang (Tsinghua Univ., China)
Page	pp. 74 - 79
Detailed information (abstract, keywords, etc)
Slides

1E-2

Title	Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm
Author	*Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang (National Yang Ming Chiao Tung Univ., Taiwan)
Page	pp. 80 - 85
Detailed information (abstract, keywords, etc)
Slides

1E-3

Title	A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench
Author	*Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng (Fudan Univ., China), Dian Zhou (Univ. of Texas, Dallas, USA)
Page	pp. 86 - 91
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 2A University Design Contest-2
Time: 10:35 - 11:10, Tuesday, January 18, 2022
Location: Room A
Chairs: Ing-Chao Lin (National Cheng Kung Univ., Taiwan), Tsung-Te Liu (National Taiwan Univ., Taiwan)

Special Feature Award
2A-1

Title	A 2.17μW@120fps Ultra-Low-Power Dual-Mode CMOS Image Sensor with Senputing Architecture
Author	*Ziwei Li (Beijing Jiaotong Univ., China), Han Xu, Zheyu Liu (Tsinghua Univ., China), Li Luo (Beijing Jiaotong Univ., China), Qi Wei, Fei Qiao (Tsinghua Univ., China)
Page	pp. 92 - 93
Detailed information (abstract, keywords, etc)
Slides

2A-2

Title	A Reconfigurable Inference Processor for Recurrent Neural Networks Based on Programmable Data Format in a Resource-Limited FPGA
Author	*Jiho Kim, Kwoanyoung Park, Tae-Hwan Kim (Korea Aerospace Univ., Republic of Korea)
Page	pp. 94 - 95
Detailed information (abstract, keywords, etc)
Slides

2A-3

Title	Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS
Author	*Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ. of Shiga Prefecture, Japan)
Page	pp. 96 - 97
Detailed information (abstract, keywords, etc)
Slides

2A-4

Title	Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication
Author	*Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai (Univ. of Tokyo, Japan)
Page	pp. 98 - 99
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2B (SS-2) Analog Circuit and Layout Synthesis: Advancement and Prospect
Time: 10:35 - 11:10, Tuesday, January 18, 2022
Location: Room B
Chair: Mark Po-Hung Lin (National Yang Ming Chiao Tung Univ., Taiwan)

2B-1

Title	(Invited Paper) AMS Circuit Synthesis Enabled by the Advancements of Circuit Architectures and ML Algorithms
Author	Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan Rasul, *Mike Shuo-Wei Chen (Univ. of Southern California, USA)
Page	pp. 100 - 107
Detailed information (abstract, keywords, etc)

2B-2

Title	(Invited Paper) Automating Analog Constraint Extraction: From Heuristics to Learning
Author	Keren Zhu, Hao Chen, Mingjie Liu, *David Z. Pan (Univ. of Texas, Austin, USA)
Page	pp. 108 - 113
Detailed information (abstract, keywords, etc)

2B-3

Title	(Invited Paper) Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead
Author	Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani (Univ. of Minnesota, USA), Mark Po-Hung Lin (National Yang Ming Chiao Tung Univ., Taiwan), *Sachin S. Sapatnekar (Univ. of Minnesota, USA)
Page	pp. 114 - 121
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 2C Low-cost and Memory-Efficient Deep Learning
Time: 10:35 - 11:10, Tuesday, January 18, 2022
Location: Room C
Chairs: Tao Liu (Lawrence Technological Univ., USA), Jianlei Yang (Beihang Univ., China)

Best Paper Candidate
2C-1

Title	PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support
Author	Chung-Hsiang Lin (Taiwan AI Lab, Taiwan), *Shao-Fu Lin (National Taiwan Univ., Taiwan), Yi-Jung Chen (National Chi Nan Univ., Taiwan), En-Yu Jenp, Chia-Lin Yang (National Taiwan Univ., Taiwan)
Page	pp. 122 - 127
Detailed information (abstract, keywords, etc)

2C-2

Title	RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search
Author	*Zheyu Yan, Weiwen Jiang, Xiaobo Sharon Hu, Yiyu Shi (Univ. of Notre Dame, USA)
Page	pp. 128 - 133
Detailed information (abstract, keywords, etc)
Slides

2C-3

Title	A Heuristic Exploration to Retraining-free Weight Sharing for CNN Compression
Author	*Etienne Dupuis (Univ Lyon, Ecole Centrale de Lyon, CNRS, INSA Lyon, Univ. Claude Bernard Lyon 1, CPE Lyon, CNRS, INL, UMR5270, France), David Novo (LIRMM, Univ. de Montpellier, CNRS, France), Ian O'Connor, Alberto Bosio (Univ Lyon, Ecole Centrale de Lyon, CNRS, INSA Lyon, Univ. Claude Bernard Lyon 1, CPE Lyon, CNRS, INL, UMR5270, France)
Page	pp. 134 - 139
Detailed information (abstract, keywords, etc)
Slides

2C-4

Title	HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation
Author	*Yao Chen (Advanced Digital Sciences Center, Singapore), Xinheng Liu (Univ. of Illinois, Urbana-Champaign, USA), Prakhar Ganesh (Advanced Digital Sciences Center, Singapore), Junhao Pan (Univ. of Illinois, Urbana-Champaign, USA), Jinjun Xiong (IBM, USA), Deming Chen (Univ. of Illinois, Urbana-Champaign, USA)
Page	pp. 140 - 146
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 2D High-level Verification and Application
Time: 10:35 - 11:10, Tuesday, January 18, 2022
Location: Room D
Chairs: Xinfei Guo (Shanghai Jiao Tong Univ., China), Hiroyuki Tomiyama (Ritsumei Univ., Japan)

2D-1

Title	Mapping Large Scale Finite Element Computing onto Wafer-Scale Engines
Author	*Yishuang Lin, Rongjian Liang, Yaguang Li, Hailiang Hu, Jiang Hu (Texas A&M Univ., USA)
Page	pp. 147 - 153
Detailed information (abstract, keywords, etc)
Slides

2D-2

Title	Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models
Author	*Yue Xing, Aarti Gupta, Sharad Malik (Princeton Univ., USA)
Page	pp. 154 - 159
Detailed information (abstract, keywords, etc)
Slides

2D-3

Title	Automated Detection of Spatial Memory Safety Violations for Constrained Devices
Author	*S�ren Tempel (Univ. of Bremen, Germany), Vladimir Herdt, Rolf Drechsler (Univ. of Bremen / DFKI GmbH, Germany)
Page	pp. 160 - 165
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2E Design for Manufacturing and Signal Integrity
Time: 10:35 - 11:10, Tuesday, January 18, 2022
Location: Room E
Chairs: Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong)

2E-1

Title	Lithography Hotspot Detection via Heterogeneous Federated Learning with Local Adaptation
Author	*Xuezhong Lin (Zhejiang Univ., China), Jingyu Pan (Duke Univ., USA), Jinming Xu (Zhejiang Univ., China), Yiran Chen (Duke Univ., USA), Cheng Zhuo (Zhejiang Univ., China)
Page	pp. 166 - 171
Detailed information (abstract, keywords, etc)

2E-2

Title	Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification
Author	*Xiqiong Bai (Fuzhou Univ., China), Ziran Zhu (Southeast Univ., China), Peng Zou, Jianli Chen, Jun Yu (Fudan Univ., China), Yao-Wen Chang (National Taiwan Univ., Taiwan)
Page	pp. 172 - 177
Detailed information (abstract, keywords, etc)

2E-3

Title	Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration
Author	*Sung-Yun Lee, Daeyeon Kim, Kyungjun Min, Seokhyeong Kang (Pohang Univ. of Science and Tech. (POSTECH), Republic of Korea)
Page	pp. 178 - 183
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 3A (DF-1) Key Drivers of Global Hardware Security
Time: 11:10 - 11:55, Tuesday, January 18, 2022
Location: Room A
Chair: Prof. Sying-Jyan Wang (National Chung Hsing Univ., Taiwan)

3A-1

Title	(Designers' Forum) Solving Chip Security�s Weakest Link: Complete Secure Boundary with PUF-based Hardware Root of Trust
Author	*John Chou (PUFSecurity, Taiwan)
Detailed information (abstract, keywords, etc)
Slides

3A-2

Title	(Designers' Forum) SoC and Data Security in the Era Of Cloud Supercomputing
Author	Dana Neustadter (Synopsys, USA), *Matthew Ma (Synopsys, China)
Detailed information (keywords, etc)

3A-3

Title	(Designers' Forum) Semiconductor Supply Chain Security-Introduction to Chip Security Test Specifications
Author	*Mars Kao (Institute for Information Industry, Taiwan)
Detailed information (keywords, etc)
Slides

[To Session Table]

Session 3B Analysis and optimization for timing, power, and reliability
Time: 11:10 - 11:55, Tuesday, January 18, 2022
Location: Room B
Chairs: Wenjian Yu (Tsinghua Univ., China), Umamaheswara Rao Tida (North Dakota State Univ., USA)

Best Paper Candidate
3B-1

Title	Pre-Routing Path Delay Estimation Based on Transformer and Residual Framework
Author	*Tai Yang, Guoqing He, Peng Cao (Southeast Univ., China)
Page	pp. 184 - 189
Detailed information (abstract, keywords, etc)
Slides

3B-2

Title	Efficient Critical Paths Search Algorithm using Mergeable Heap
Author	Kexing Zhou, *Zizheng Guo (Peking Univ., China), Tsung-Wei Huang (Univ. of Utah, USA), Yibo Lin (Peking Univ., China)
Page	pp. 190 - 195
Detailed information (abstract, keywords, etc)
Slides

3B-3

Title	A Graph Neural Network Method for Fast ECO Leakage Power Optimization
Author	*Kai Wang, Peng Cao (Southeast Univ., China)
Page	pp. 196 - 201
Detailed information (abstract, keywords, etc)

3B-4

Title	Vector-based Dynamic IR-drop Prediction Using Machine Learning
Author	Jia-Xian Chen, Shi-Tang Liu, *Yu-Tsung Wu, Mu-Ting Wu, Chien-Mo Li (National Taiwan Univ., Taiwan), Norman Chang, Ying-Shiun Li (Ansys, USA), Wen-Tze Chuang (Ansys, Taiwan)
Page	pp. 202 - 207
Detailed information (abstract, keywords, etc)
Slides

3B-5

Title	Fast Electromigration Stress Analysis Considering Spatial Joule Heating Effects
Author	*Mohammadamir Kavousi, Liang Chen, Sheldon Tan (Univ. of California, Riverside, USA)
Page	pp. 208 - 213
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 3C Advanced Machine Learning with Emerging Technologies
Time: 11:10 - 11:55, Tuesday, January 18, 2022
Location: Room C
Chairs: Fan Chen (Indiana Univ. Bloomington, USA), Zhuwei Qin (San Francisco State Univ., USA)

3C-1

Title	SONIC: A Sparse Neural Network Inference Accelerator with Silicon Photonics for Energy-Efficient Deep Learning
Author	*Febin Payickadu (Sunny, USA), Mahdi (Nikdast, USA), Sudeep (Pasricha, USA)
Page	pp. 214 - 219
Detailed information (abstract, keywords, etc)
Slides

3C-2

Title	XCelHD: An Efficient GPU-Powered Hyperdimensional Computing with Parallelized Training
Author	*Jaeyoung Kang, Behnam Khaleghi (Univ. of California, San Diego, USA), Yeseong Kim (DGIST, Republic of Korea), Tajana Rosing (Univ. of California, San Diego, USA)
Page	pp. 220 - 225
Detailed information (abstract, keywords, etc)

3C-3

Title	HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine
Author	*Qidong Tang, Zhezhi He, Fangxin Liu, Zongwu Wang, Yiyuan Zhou, Yinghuan Zhang, Li Jiang (Shanghai Jiao Tong Univ., China)
Page	pp. 226 - 231
Detailed information (abstract, keywords, etc)
Slides

3C-4

Title	SynthNet: A High-throughput yet Energy-efficient Combinational Logic Neural Network
Author	*Tianen Chen, Taylor Kemp, Younghyun Kim (Univ. of Wisconsin, USA)
Page	pp. 232 - 237
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 3D Software Solutions for Heterogeneous Embedded Architectures
Time: 11:10 - 11:55, Tuesday, January 18, 2022
Location: Room D
Chairs: Sara Vinco (Politecnico di Torino, Italy), Jason Xue (Hong Kong City Univ., Hong Kong)

Best Paper Award
3D-1

Title	Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems
Author	*Zerun Li, Xiaoming Chen, Yinhe Han (Chinese Academy of Sciences, China)
Page	pp. 238 - 243
Detailed information (abstract, keywords, etc)

3D-2

Title	Boosting the Search Performance of B+-tree with Sentinels for Non-volatile Memory
Author	*Chongnan Ye, Chundong Wang (ShanghaiTech Univ., China)
Page	pp. 244 - 249
Detailed information (abstract, keywords, etc)
Slides

3D-3

Title	Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator
Author	*Hongxiang Fan (Imperial College London, UK), Martin Ferianc (Univ. College London, UK), Zhiqiang Que (Imperial College London, UK), He Li (Cambridge Univ., UK), Shuanglong Liu (Hunan Normal Univ.,, China), Xinyu Niu (Corerain Technologies, China), Wayne Luk (Imperial College London, UK)
Page	pp. 250 - 255
Detailed information (abstract, keywords, etc)
Slides

3D-4

Title	Exploring ILP for VLIW architecture by Quantified Modeling and Dynamic Programming-based Instruction Scheduling
Author	*Can Deng, Zhaoyun Chen, Yang Shi, Xichang Kong, Mei Wen (National Univ. of Defense Tech., China)
Page	pp. 256 - 261
Detailed information (abstract, keywords, etc)
Slides

3D-5

Title	Time-Triggered Scheduling for Time-Sensitive Networking with Preemption
Author	*Yuanbin Zhou (Linkoping Univ., Sweden), Soheil Samii (Linkoping Univ./General Motors, Sweden), Petru Eles, Zebo Peng (Linkoping Univ., Sweden)
Page	pp. 262 - 267
Detailed information (abstract, keywords, etc)

Wednesday, January 19, 2022

[To Session Table]

Session 2K Keynote Session II
Time: 9:00 - 10:00, Wednesday, January 19, 2022
Location: Room S
Chair: Masanori Hashimoto (Kyoto Univ., Japan)

2K-1

Title	(Keynote Address) Powering a Quantum Future through Quantum Circuits
Author	*Jerry M. Chow (IBM, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4A (SS-3) Technology Advancements inside the Edge Computing Paradigm and using the Machine Learning Techniques
Time: 10:00 - 10:35, Wednesday, January 19, 2022
Location: Room A
Chair: Sabya Das (Synopsys, USA)

4A-1

Title	(Invited Paper) A Task Parallelism Runtime Solution for Deep Learning Applications using MPSoC on Edge Devices
Author	Hua Jiang (Xilinx Inc, USA), Raghav Chakravarthy (Centennial High School, USA), *Ravikumar V Chakaravarthy (Xilinx Inc, USA)
Page	pp. 268 - 274
Detailed information (abstract, keywords, etc)
Slides

4A-2

Title	(Invited Paper) Circuit and System Technologies for Energy-Efficient Edge Robotics
Author	*Zishen Wan, Ashwin Sanjay Lele, Arijit Raychowdhury (Georgia Tech, USA)
Page	pp. 275 - 280
Detailed information (abstract, keywords, etc)
Slides

4A-3

Title	(Invited Paper) RTL Regression Test Selection using Machine Learning
Author	*Ganapathy Parthasarathy (Synopsys Inc, USA), Aabid Rushdi (Synopsys Inc, Sri Lanka), Parivesh Choudhary, Saurav Nanda (Synopsys Inc, USA), Malan Evans, Hansika Gunasekara (Synopsys Inc, Sri Lanka), Sridhar Rajakumar (Synopsys Inc, USA)
Page	pp. 281 - 287
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 4B Recent Advances in Placement Techniques
Time: 10:00 - 10:35, Wednesday, January 19, 2022
Location: Room B
Chairs: Jinwook Jung (IBM Research, USA), Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)

Best Paper Award
4B-1

Title	Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization
Author	Chung-Kuan Cheng, Chia-Tung Ho, *Chester Holtz (Univ. of California, San Diego, USA)
Page	pp. 288 - 293
Detailed information (abstract, keywords, etc)
Slides

4B-2

Title	HybridGP: Global Placement for Hybrid-Row-Height Designs
Author	Kuan-Yu Chen, *Hsiu-Chu Hsu, Wai-Kei Mak, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 294 - 299
Detailed information (abstract, keywords, etc)

4B-3

Title	DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
Author	*Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang (Univ. of Texas, Austin, USA), Mahesh Iyer (Intel, USA), David Z. Pan (Univ. of Texas, Austin, USA)
Page	pp. 300 - 306
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 4C Emerging Trends in Stochastic Computing
Time: 10:00 - 10:35, Wednesday, January 19, 2022
Location: Room C
Chairs: Xunzhao Yin (Zhejiang Univ., China), Lang Feng (Nanjing Univ., China)

4C-1

Title	Linear Feedback Shift Register Reseeding for Stochastic Circuit Repairing and Minimization
Author	*Chen Wang, Weikang Qian (Shanghai Jiao Tong Univ., China)
Page	pp. 307 - 313
Detailed information (abstract, keywords, etc)
Slides

4C-2

Title	BSC: Block-based Stochastic Computing to Enable Accurate and Efficient TinyML
Author	*Yuhong Song, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Rui Xu, Yongzhuo Zhang (East China Normal Univ., China), Bingzhe Li (Oklahoma State Univ., USA), Lei Yang (Univ. of New Mexico, USA)
Page	pp. 314 - 319
Detailed information (abstract, keywords, etc)
Slides

4C-3

Title	Streaming Accuracy: Characterizing Early Termination in Stochastic Computing
Author	*Hsuan Hsiao (Univ. of Toronto, Canada), Joshua San Miguel (Univ. of Wisconsin-Madison, USA), Jason Anderson (Univ. of Toronto, Canada)
Page	pp. 320 - 325
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 4D Efficient Techniques for Emerging Applications
Time: 10:00 - 10:35, Wednesday, January 19, 2022
Location: Room D
Chairs: Xueqing Li (Tsinghua Univ., China), Sangyoung Park (Tech. Univ. Berlin, Germany)

Best Paper Candidate
4D-1

Title	TENET: Temporal CNN with Attention for Anomaly Detection in Automotive Cyber-Physical Systems
Author	*Sooryaa Vignesh Thiruloga, Vipin Kumar Kukkala, Sudeep Pasricha (Colorado State Univ., USA)
Page	pp. 326 - 331
Detailed information (abstract, keywords, etc)
Slides

4D-2

Title	ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement
Author	*Hanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray Chen, David Pan (Univ. of Texas, Austin, USA)
Page	pp. 332 - 338
Detailed information (abstract, keywords, etc)
Slides

4D-3

Title	Solving Least-Squares Fitting in O(1) Using RRAM-based Computing-in-Memory Technique
Author	*Xiaoming Chen, Yinhe Han (Chinese Academy of Sciences, China)
Page	pp. 339 - 344
Detailed information (abstract, keywords, etc)
Slides

4D-4

Title	SonicFFT: A system architecture for ultrasonic-based FFT acceleration
Author	Darayus Adil Patel (Nanyang Technological Univ., Singapore), Viet Phuong Bui (Institute of High Performance Computing, ASTAR (Agency for Science, Technology and Research), Singapore), Kevin Tshun Chuan Chai (Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Singapore), Amit Lal (Cornell Univ., USA), Mohamed M. Sabry Aly (Nanyang Technological Univ., Singapore)
Page	pp. 345 - 351
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 5A (DF-2) Compiler and Toolchain for Efficient AI Computation
Time: 10:35 - 11:10, Wednesday, January 19, 2022
Location: Room A
Chair: Chia-Heng Tu (National Cheng Kung Univ., Taiwan)

5A-1

Title	(Designers' Forum) Making Deep Learning More Portable with Deep Learning Compiler
Author	*Cody Yu (Amazon Web Services, USA)
Detailed information (abstract, keywords, etc)
Slides

5A-2

Title	(Designers' Forum) Tiny ONNC: MLIR-based AI Compiler for ARM IoT Devices
Author	*Luba Tang (Skymizer Taiwan, Taiwan)
Detailed information (abstract, keywords, etc)

5A-3

Title	(Designers' Forum) Architecture Design for the DNN Accelerator
Author	*Yao-Hua Chen (ITRI, Taiwan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5B Moving frontiers of test and simulation
Time: 10:35 - 11:10, Wednesday, January 19, 2022
Location: Room B
Chairs: Ying Zhang (Tongji Univ., China), Michihiro Shintani (NAIST, Japan)

5B-1

Title	FIRVER: Concolic Testing for Systematic Validation of Firmware Binaries
Author	*Tashfia Alam (Univ. of Florida, USA), Zhenkun Yang, Bo Chen, Nicholas Armour (Intel, USA), Sandip Ray (Univ. of Florida, USA)
Page	pp. 352 - 357
Detailed information (abstract, keywords, etc)

5B-2

Title	WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging
Author	*Lucas Klemmer, Daniel Gro�e (Johannes Kepler Univ. Linz, Austria)
Page	pp. 358 - 364
Detailed information (abstract, keywords, etc)
Slides

5B-3

Title	Accelerate SAT-based ATPG via Preprocessing and New Conflict Management Heuristics
Author	Junhua Huang (Xiamen Univ., China), *Hui-Ling Zhen (Noah's Ark Lab, Huawei, China), Naixing Wang (Hisilicon, Huawei, China), Mingxuan Yuan, Hui Mao (Noah's Ark Lab, Huawei, China), Yu Huang (Hisilicon, Huawei, China), Jiping Tao (Xiamen Univ., China)
Page	pp. 365 - 370
Detailed information (abstract, keywords, etc)
Slides

5B-4

Title	A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine Learning
Author	*Mohamed Saleh Abouelyazid (American Univ. in Cairo, Egypt), Sherif Hammouda (Siemens EDA, Egypt), Yehea Ismail (American Univ. in Cairo, Egypt)
Page	pp. 371 - 376
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 5C Optimizations in Modern Memory Architecture
Time: 10:35 - 11:10, Wednesday, January 19, 2022
Location: Room C
Chairs: Chenchen Fu (Southeast Unviersity, China), Shouzhen Gu (East China Normal Univ., China)

Best Paper Candidate
5C-1

Title	Lamina: Low Overhead Wear Leveling for NVM with Bounded Tail
Author	*Jiacheng Huang, Min Peng, Libing Wu (Wuhan Univ., China), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong), Qingan Li (Wuhan Univ., China)
Page	pp. 377 - 382
Detailed information (abstract, keywords, etc)
Slides

5C-2

Title	Heterogeneous Memory Architecture Accommodating Processing-In-Memory on SoC For AIoT Applications
Author	*Kangyi Qiu (Peking Univ., China), Yaojun Zhang (Pimchip Technology, China), Bonan Yan, Ru Huang (Peking Univ., China)
Page	pp. 383 - 388
Detailed information (abstract, keywords, etc)
Slides

5C-3

Title	Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete Memory Latency Hiding
Author	*Rui Xu, Edwin Hsing.-Mean Sha, Qingfeng Zhuge, Yuhong Song, Jingzhi Lin (East China Normal Univ., China)
Page	pp. 389 - 394
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 5D Novel Boolean Optimization and Mapping
Time: 10:35 - 11:10, Wednesday, January 19, 2022
Location: Room D
Chairs: Shinji Kimura (Waseda Univ., Japan), Kenshu Seto (Tokyo City Univ., Japan)

5D-1

Title	Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis
Author	Heinz Riener, *Siang-Yun Lee (EPFL, Switzerland), Alan Mishchenko (UC Berkeley, USA), Giovanni de Micheli (EPFL, Switzerland)
Page	pp. 395 - 402
Detailed information (abstract, keywords, etc)
Slides

5D-2

Title	Delay Optimization of Combinational Logic by And-Or Path Restructuring
Author	*Ulrich Brenner (Univ. of Bonn, Germany), Anna Silvanus (Synopsys GmbH, Germany)
Page	pp. 403 - 409
Detailed information (abstract, keywords, etc)
Slides

5D-3

Title	A Versatile Mapping Approach for Technology Mapping and Graph Optimization
Author	*Alessandro Tempia Calvino, Heinz Riener (EPFL, Switzerland), Shubham Rai, Akash Kumar (TU Dresden, Germany), Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 410 - 416
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 6A (DF-3) AI for Chip Design and Testing
Time: 11:10 - 11:45, Wednesday, January 19, 2022
Location: Room A
Chair: Ing-Chao Lin (National Cheng Kung Univ., Taiwan)

6A-1

Title	(Designers' Forum) Reinforcement Learning-Driven Optimization for Superior Performance, Power and Productivity in Chip Design
Author	*Thomas Andersen (Synopsys, USA)
Detailed information (abstract, keywords, etc)
Slides

6A-2

Title	(Designers' Forum) Machine Learning for Electronic Design Automation
Author	*Erick Chao (Cadence, Taiwan)
Detailed information (abstract, keywords, etc)
Slides

6A-3

Title	(Designers' Forum) Fast Reward Calculation for Reinforcement Learning Macro Placement
Author	*Tung-Chieh Chen (Maxeda Technology, Taiwan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6B Towards Reliable and Secure Circuits: Cross Perspectives
Time: 11:10 - 11:45, Wednesday, January 19, 2022
Location: Room B
Chairs: Kaveh Shamsi (Univ. of Texas, Dallas, USA), Xiaolong Guo (Kansas State Univ., USA)

6B-1

Title	Avatar: Reinforcing Fault Attack Countermeasures in EDA with Fault Transformations
Author	*Prithwish Basu Roy (IIT Madras, India), Patanjali SLPSK (Univ. of Florida, USA), Chester Rebeiro (IIT Madras, India)
Page	pp. 417 - 422
Detailed information (abstract, keywords, etc)
Slides

6B-2

Title	Anti-Piracy of Analog and Mixed-Signal Circuits in FD-SOI
Author	*Mariam Tlili, Alhassan Sayed, Doaa Mahmoud, Marie-Minerve Louerat, Hassan Aboushady, Haralampos-G. Stratigopoulos (Sorbonne Univ., CNRS, LIP6, France)
Page	pp. 423 - 428
Detailed information (abstract, keywords, etc)
Slides

6B-3

Title	Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques
Author	*Sajjad Parvin (Univ. of Bremen, Germany), Thilo Krachenfels (Tech. Univ. Berlin, Germany), Shahin Tajik (Worcester Polytechnic Institute, USA), Jean-Pierre Seifert (Tech. Univ. Berlin, Germany), Frank Sill Torres (German Aerospace Center (DLR), Germany), Rolf Drechsler (Univ. of Bremen, Germany)
Page	pp. 429 - 435
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 6C Accelerator Architectures for Machine Learning
Time: 11:10 - 11:45, Wednesday, January 19, 2022
Location: Room C
Chairs: Linghao Song (Univ. of California, Los Angeles, USA), Bonan Yan (Peking Univ., China)

Best Paper Candidate
6C-1

Title	Dynamic CNN Accelerator Supporting Efficient Filter Generator with Kernel Enhancement and Online Channel Pruning
Author	*Chen Tang, Wenyu Sun, Wenxun Wang, Yongpan Liu (Tsinghua Univ., China)
Page	pp. 436 - 441
Detailed information (abstract, keywords, etc)
Slides

6C-2

Title	Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation
Author	*Yixiong Yang, Ruoyang Liu, Wenyu Sun, Jinshan Yue, Huazhong Yang, Yongpan Liu (Tsinghua Univ., China)
Page	pp. 442 - 447
Detailed information (abstract, keywords, etc)
Slides

6C-3

Title	An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks
Author	*Liuyao Dai, Quan Cheng, Yuhang Wang, Gengbin Huang, Junzhuo Zhou, Kai Li, Wei Mao, Hao Yu (Southern Univ. of Science and Tech., China)
Page	pp. 448 - 453
Detailed information (abstract, keywords, etc)
Slides

6C-4

Title	Multi-Precision Deep Neural Network Acceleration on FPGAs
Author	*Negar Neda (Univ. of Tehran, Iran), Salim Ullah (TU Dresden, Germany), Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi (UT, Iran), Akash Kumar (TU Dresden, Germany)
Page	pp. 454 - 459
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 6D Quantum and Reconfigurable Computing
Time: 11:10 - 11:45, Wednesday, January 19, 2022
Location: Room D
Chairs: Michael Miller (Univ. of Victoria, Canada), Shigeru Yamashita (Ritsumeikan Univ., Japan)

6D-1

Title	Efficient Preparation of Cyclic Quantum States
Author	*Fereshte Mozafari (EPFL, Switzerland), Yuxiang Yang (ETH, Switzerland), Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 460 - 465
Detailed information (abstract, keywords, etc)
Slides

6D-2

Title	Limiting the Search Space in Optimal Quantum Circuit Mapping
Author	*Lukas Burgholzer, Sarah Schneider, Robert Wille (Johannes Kepler Univ. Linz, Austria)
Page	pp. 466 - 471
Detailed information (abstract, keywords, etc)
Slides

6D-3

Title	Efficient Routing in Coarse-Grained Reconfigurable Arrays using Multi-Pole NEM Relays
Author	*Akash Levy, Michael Oduoza, Akhilesh Balasingam, Roger T. Howe, Priyanka Raina (Stanford Univ., USA)
Page	pp. 472 - 478
Detailed information (abstract, keywords, etc)
Slides

6D-4

Title	Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs
Author	*Kangwei Xu, Yuanqing Cheng (Beihang Univ., China)
Page	pp. 479 - 484
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 1W Cadence Training Workshop
Time: 13:30 - 16:30, Wednesday, January 19, 2022
Location: Room W
Chair: Milton Lien (Cadence, Taiwan)

1W-1 (Time: 13:30 - 14:10)

Title	(Training Workshop) (AWR) PA: Loadpull & Matching Synthesis, GaN PA Design with Thermal Analysis
Author	*Milton Lien (Cadence, Taiwan)
Detailed information (abstract, keywords, etc)

1W-2 (Time: 14:10 - 14:50)

Title	(Training Workshop) (EMX/Virtuoso RF): EM Extraction/Modeling of Passive Components in RFIC/ Integrated Flow with RFIC Simulation Platform
Author	*Milton Lien (Cadence, Taiwan)
Detailed information (abstract, keywords, etc)

1W-3 (Time: 14:50 - 15:30)

Title	(Training Workshop) (Sigrity Electro-Thermal PI): Die Model Aware Target Impedance Exploration Using SystemPI
Author	*Eric Chen (Cadence, Taiwan)
Detailed information (abstract, keywords, etc)

1W-4 (Time: 15:30 - 16:10)

Title	(Training Workshop) (Sigrity SI): How to Design GDDR6 to Improve Performance and Efficiency
Author	*Homer Chang (Cadence, Taiwan)
Detailed information (abstract, keywords, etc)

Thursday, January 20, 2022

[To Session Table]

Session 3K Keynote Session III
Time: 9:00 - 10:00, Thursday, January 20, 2022
Location: Room S
Chair: Wai-Kei Mak (National Tsing Hua Univ., Taiwan)

3K-1

Title	(Keynote Address) EDA Opportunities for Future HPC and 3D IC Integration
Author	*Ken Wang (TSMC, Taiwan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7A (SS-4) Reshaping the Future of Physical and Circuit Design, Power and Memory with Machine Learning
Time: 10:00 - 10:35, Thursday, January 20, 2022
Location: Room A
Chair: Taeyoung Kim (Intel, USA)

7A-1

Title	(Invited Paper) Fast Thermal Analysis for Chiplet Design based on Graph Convolution Networks
Author	*Liang Chen, Wentian Jin, Sheldon Tan (Univ. of California, Riverside, USA)
Page	pp. 485 - 492
Detailed information (abstract, keywords, etc)
Slides

7A-2

Title	(Invited Paper) Design Close to the Edge for Advanced Technology using Machine Learning and Brain-inspired Algorithms
Author	Hussam Amrouch, Florian Klemme, *Paul R. Genssler (Univ. of Stuttgart, Germany)
Page	pp. 493 - 499
Detailed information (abstract, keywords, etc)
Slides

7A-3

Title	(Invited Paper) Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives
Author	Ahmet F. Budak, Zixuan Jiang, Keren Zhu (Univ. of Texas, Austin, USA), Azalia Mirhoseini, Anna Goldie (Google, USA), *David Z. Pan (Univ. of Texas, Austin, USA)
Page	pp. 500 - 505
Detailed information (abstract, keywords, etc)

7A-4

Title	(Invited Paper) Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level
Author	Felix Last (Tech. Univ. of Munich, Germany), Ceren Yeni (Intel Germany, Germany), *Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Page	pp. 506 - 512
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 7B Advances in Analog Design Methodologies
Time: 10:00 - 10:35, Thursday, January 20, 2022
Location: Room B
Chairs: Markus Olbrich (Univ. of Hannover, Germany), Ian O'Connor (Ecole Centrale de Lyon, France)

7B-1

Title	Transient Adjoint DAE Sensitivities: a Complete, Rigorous, and Numerically Accurate Formulation
Author	*Naomi Sagan, Jaijeet Roychowdhury (Univ. of California, Berkeley, USA)
Page	pp. 513 - 518
Detailed information (abstract, keywords, etc)
Slides

7B-2

Title	Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits
Author	*Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan (Univ. of Texas, Austin, USA)
Page	pp. 519 - 525
Detailed information (abstract, keywords, etc)
Slides

7B-3

Title	TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture
Author	*Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan Rasul, Mike Shuo-Wei Chen (Univ. of Southern California, USA)
Page	pp. 526 - 531
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 7C Low-Energy Edge AI Computing
Time: 10:00 - 10:35, Thursday, January 20, 2022
Location: Room C
Chairs: Bing Li (Capital Normal Univ., China), Yaojun Zhang (Pimchip Technology Co., China)

7C-1

Title	Efficient Computer Vision on Edge Devices with Pipeline-Parallel Hierarchical Neural Networks
Author	*Abhinav Goel, Caleb Tung, Xiao Hu (Purdue Univ., USA), George K. Thiruvathukal (Loyola Univ. Chicago, USA), James C. Davis, Yung-Hsiang Lu (Purdue Univ., USA)
Page	pp. 532 - 537
Detailed information (abstract, keywords, etc)

7C-2

Title	Efficient On-Device Incremental Learning by Weight Freezing
Author	*Ze-Han Wang, Zhenli He, Hui Fang, Yi-Xiong Huang, Ying Sun, Yu Yang, Zhi-Yuan Zhang, Di Liu (Yunnan Univ., China)
Page	pp. 538 - 543
Detailed information (abstract, keywords, etc)
Slides

7C-3

Title	EdgeⁿAI: Distributed Inference with Local Edge Devices and Minimum Latency
Author	Maedeh Hemmat, *Azadeh Davoodi, Yu Hen Hu (Univ. of Wisconsin-Madison, USA)
Page	pp. 544 - 549
Detailed information (abstract, keywords, etc)
Slides

7C-4

Title	Large Forests and Where to �Partially� Fit Them
Author	*Andrea Damiani, Emanuele Del Sozzo, Marco D. Santambrogio (Politecnico di Milano, Italy)
Page	pp. 550 - 555
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 7D Emerging Technologies in Embedded Systems and Cyber-Physical Systems
Time: 10:00 - 10:35, Thursday, January 20, 2022
Location: Room D
Chairs: Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Shiyan Hu (Univ. of Southampton, UK)

7D-1

Title	AdaSens: Adaptive Environment Monitoring by Coordinating Intermittently-Powered Sensors
Author	Shuyue Lan, *Zhilu Wang, John Mamish, Josiah Hester, Qi Zhu (Northwestern Univ., USA)
Page	pp. 556 - 561
Detailed information (abstract, keywords, etc)
Slides

7D-2

Title	Energy Harvesting Aware Multi-hop Routing Policy in Distributed IoT System Based on Multi-agent Reinforcement Learning
Author	*Wen Zhang (Texas A&M Univ.- Corpus Christi, USA), Tao Liu (Lawrence Technological Univ., USA), Mimi Xie (Univ. of Texas, San Antonio, USA), Longzhuang Li, Dulal Kar, Chen Pan (Texas A&M Univ.- Corpus Christi, USA)
Page	pp. 562 - 567
Detailed information (abstract, keywords, etc)

7D-3

Title	An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers
Author	*Lingxiao Hou, Yutaka Masuda, Tohru Ishihara (Nagoya Univ., Japan)
Page	pp. 568 - 573
Detailed information (abstract, keywords, etc)
Slides

7D-4

Title	Neural Network Pruning and Fast Training for DRL-based UAV Trajectory Planning
Author	Yilan Li, Haowen Fang, *Mingyang Li, Yue Ma, Qinru Qiu (Syracuse Univ., USA)
Page	pp. 574 - 579
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 8A (DF-4) Empowering AI through Innovative Computing
Time: 10:35 - 11:10, Thursday, January 20, 2022
Location: Room A
Chair: Prof. Chao-Tsung Huang (National Tsing Hua Univ., Taiwan)

8A-1

Title	(Designers' Forum) Mediatek Dual-Core Deep-Learning Accelerator for Versatile AI Applications
Author	*Chih-Chung Cheng (Mediatek, Taiwan)
Detailed information (abstract, keywords, etc)
Slides

8A-2

Title	(Designers' Forum) Kneron KL-530 introduction - How we define the next generation of Edge AI Chip
Author	*David Yang (Kneron, USA)
Detailed information (abstract, keywords, etc)
Slides

8A-3

Title	(Designers' Forum) In-Memory Computing for Future AI Acceleration
Author	*Tuo-Hung Hou (National Yang Ming Chiao Tung Univ., Taiwan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8B Advances in VLSI Routing
Time: 10:35 - 11:10, Thursday, January 20, 2022
Location: Room B
Chairs: Wuxi Li (Xilinx, USA), Yi-Lang Li (National Yang Ming Chiao Tung Univ., Taiwan)

8B-1

Title	High-Correlation 3D Routability Estimation for Congestion-guided Global Routing
Author	*Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou (Fuzhou Univ., China), Zhonghua Zhou (Univ. of British Columbia, Canada), Yilu Chen (Fuzhou Univ., China), Jianli Chen (Fudan Univ., China), Yao-Wen Chang (National Taiwan Univ., Taiwan)
Page	pp. 580 - 585
Detailed information (abstract, keywords, etc)
Slides

8B-2

Title	SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity
Author	*Jiayuan He (Univ. of Texas, Austin, USA), Udit Agarwal (Katana Graph, USA), Yihang Yang, Rajit Manohar (Yale Univ., USA), Keshav Pingali (Univ. of Texas, Austin, USA)
Page	pp. 586 - 591
Detailed information (abstract, keywords, etc)
Slides

8B-3

Title	FPGA-Accelerated Maze Routing Kernel for VLSI Designs
Author	*Xun Jiang (Nanjing Univ., China), Jiarui Wang, Yibo Lin (Peking Univ., China), Zhongfeng Wang (Nanjing Univ., China)
Page	pp. 592 - 597
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 8C Machine Learning with Crossbar Memories
Time: 10:35 - 11:10, Thursday, January 20, 2022
Location: Room C
Chairs: Ing-chao Lin (National Cheng Kung Univ., Taiwan), Yi-Jung Chen (National Chi Nan Univ., Taiwan)

8C-1

Title	Reliable Memristive Neural Network Accelerators Based on Early Denoising and Sparsity Induction
Author	*Anlan Yu, Ning Lyu, Wujie Wen, Zhiyuan Yan (Lehigh Univ., USA)
Page	pp. 598 - 603
Detailed information (abstract, keywords, etc)
Slides

8C-2

Title	Boosting ReRAM-based DNN by Row Activation Oversubscription
Author	Mengyu Guo, Zihan Zhang, Jianfei Jiang, Qin Wang, *Naifeng Jing (Shanghai Jiao Tong Univ., China)
Page	pp. 604 - 609
Detailed information (abstract, keywords, etc)
Slides

8C-3

Title	XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption
Author	*Fan Zhang, Li Yang, Jian Meng, Yu (Kevin) Cao, Jae-sun Seo, Deliang Fan (Arizona State Univ., USA)
Page	pp. 610 - 615
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 8D High Level Synthesis, CGRA mapping and P&R for hotspot mitigation
Time: 10:35 - 11:10, Thursday, January 20, 2022
Location: Room D
Chairs: Shinya Takamaeda-Yamazaki (Univ. of Tokyo, Japan), Kazutoshi Wakabayashi (Univ. of Tokyo, Japan)

8D-1

Title	CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams
Author	*Rami Beidas, Jason H. Anderson (Univ. of Toronto, Canada)
Page	pp. 616 - 622
Detailed information (abstract, keywords, etc)
Slides

8D-2

Title	Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS
Author	*Md Imtiaz Rashid, Benjamin Carrion Schaefer (Univ. of Texas, Dallas, USA)
Page	pp. 623 - 628
Detailed information (abstract, keywords, etc)
Slides

8D-3

Title	Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling
Author	*Benjamin Carrion Schaefer (Univ. of Texas, Dallas, USA)
Page	pp. 629 - 634
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 9A (SS-5) Artificial Intelligence on Back-End EDA: Panacea or One-Trick Pony?
Time: 11:10 - 11:45, Thursday, January 20, 2022
Location: Room A
Chair: Yibo Lin (Peking Univ., China)

9A-1

Title	(Invited Paper) Techniques for CAD Tool Parameter Auto-tuning in Physical Synthesis: A Survey
Author	*Hao Geng, Tinghuan Chen, Qi Sun, Bei Yu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 635 - 640
Detailed information (abstract, keywords, etc)
Slides

9A-2

Title	(Invited Paper) Application of Deep Learning in Back-End Simulation: Challenges and Opportunities
Author	Yufei Chen (Zhejiang Univ., China), Haojie Pei (China Univ. of Petroleum, China), Xiao Dong (Zhejiang Univ., China), Zhou Jin (China Univ. of Petroleum, China), *Cheng Zhuo (Zhejiang Univ., China)
Page	pp. 641 - 646
Detailed information (abstract, keywords, etc)

9A-3

Title	(Invited Paper) EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator using a Canonical Architectural Representation
Author	Jiaxi Zhang, Qiuyang Gao, Yijiang Guo, Bizhao Shi, *Guojie Luo (Peking Univ., China)
Page	pp. 647 - 653
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9B Side Channel Leakage: Characterization and Protection
Time: 11:10 - 11:45, Thursday, January 20, 2022
Location: Room B
Chairs: Xueyan Wang (Beihang Univ., China), Bi Wu (Nanjing Univ. of Aeronautics and Astronautics, China)

Best Paper Candidate
9B-1

Title	DVFSspy: Using Dynamic Voltage and Frequency Scaling As A Covert Channel for Multiple Procedures
Author	*Pengfei Qiu, Dongsheng Wang, Yongqiang Lyu (Tsinghua Univ., China), Gang Qu (Univ. of Maryland, USA)
Page	pp. 654 - 659
Detailed information (abstract, keywords, etc)
Slides

9B-2

Title	Fortify: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs
Author	*Lakshmy A V, Chester Rebeiro (Indian Inst. of Tech. Madras, India), Swarup Bhunia (Univ. of Florida, USA)
Page	pp. 660 - 665
Detailed information (abstract, keywords, etc)
Slides

9B-3

Title	Data Leakage through Self-Terminated Write Schemes in Memristive Caches
Author	*Jonas Krautter, Mahta Mayahinia, Dennis R. E. Gnad, Mehdi B. Tahoori (Karlsruhe Inst. of Tech. (KIT), Germany)
Page	pp. 666 - 671
Detailed information (abstract, keywords, etc)
Slides

9B-4

Title	A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber
Author	*Jianan Mu, Yixuan Zhao (Chinese Academy of Sciences, China), Zongyue Wang (Open Security Research, China), Jing Ye (Chinese Academy of Sciences, China), Junfeng Fan (Open Security Research, China), Shuai Chen (Rock-Solid Security Lab, Fiberhome, China), Huawei Li, Xiaowei Li (Chinese Academy of Sciences, China), Yuan Cao (Hohai Univ., China)
Page	pp. 672 - 677
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 9C Emerging Non-volatile Memory-based In-Memory Computing
Time: 11:10 - 11:45, Thursday, January 20, 2022
Location: Room C
Chairs: Ken Takeuchi (Univ. of Tokyo, Japan), Tae Hyoung Kim (Nanyang Technology Univ., Singapore)

9C-1

Title	FeMIC: Multi-Operands In-Memory Computing Based on FeFETs
Author	*Rui Liu (Xiangtan Univ., China), Xiaoyu Zhang, Xiaoming Chen, Yinhe Han (Chinese Academy of Sciences, China), Minghua Tang (Xiangtan Univ., China)
Page	pp. 678 - 683
Detailed information (abstract, keywords, etc)

9C-2

Title	Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC
Author	*Yuxuan Huang, Yifan He (Tsinghua Univ., China), Jinshan Yue (Chinese Academy of Sciences, China), Wenyu Sun, Huazhong Yang, Yongpan Liu (Tsinghua Univ., China)
Page	pp. 684 - 689
Detailed information (abstract, keywords, etc)

9C-3

Title	STREAM: Towards READ-based In-Memory Computing for Streaming based Data Processing
Author	*Muhammad Rashedul Haq Rashed, Sven Thijssen (Univ. of Central Florida, USA), Sumit Kumar Jha (Univ. of Texas, San Antonio, USA), Fan Yao, Rickard Ewetz (Univ. of Central Florida, USA)
Page	pp. 690 - 695
Detailed information (abstract, keywords, etc)
Slides

[To Session Table]

Session 9D System Level Design of Learning Systems
Time: 11:10 - 11:45, Thursday, January 20, 2022
Location: Room D
Chairs: Chun-Yi Lee (National Tsing Hua Univ., Taiwan), Vasily Moshnyaga (Fukuoka Univ., Japan)

9D-1

Title	On the Viability of Decision Trees for Learning Models of Systems
Author	*Swantje Plambeck, Lutz Schammer, G�rschwin Fey (Hamburg Univ. of Tech., Germany)
Page	pp. 696 - 701
Detailed information (abstract, keywords, etc)
Slides

Best Paper Candidate
9D-2

Title	This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator
Author	*Yen-Ting Tsou (National Taiwan Univ., Taiwan), Kuan-Hsun Chen (Univ. of Twente, Netherlands), Chia-Lin Yang (National Taiwan Univ., Taiwan), Hsiang-Yun Cheng (Academia Sinica, Taiwan), Jian-Jia Chen (Tech. Univ. Dortmund, Germany), Der-Yu Tsai (National Taiwan Univ., Taiwan)
Page	pp. 702 - 707
Detailed information (abstract, keywords, etc)
Slides

9D-3

Title	HACScale: Hardware-Aware Compound Scaling for Resource-Efficient DNNs
Author	*Hao Kong, Di Liu, Xiangzhong Luo, Weichen Liu (Nanyang Technological Univ., Singapore), Ravi Subramaniam (HP, USA)
Page	pp. 708 - 713
Detailed information (abstract, keywords, etc)
Slides

9D-4

Title	Pearl: Towards Optimization of DNN-accelerators Via Closed-Form Analytical Representation
Author	*Arko Dutt, Suprojit Nandy, Mohamed M Sabry (NTU Singapore, Singapore)
Page	pp. 714 - 719
Detailed information (abstract, keywords, etc)
Slides

The 27th Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of papers

The 27th Asia and South Pacific Design Automation Conference
Technical Program